//////////////////////////////////////////////////////////////////////////////////
//				Instruction Memory				//
//						    reference : lecure ppt	//
//////////////////////////////////////////////////////////////////////////////////


module IMEM(iClk,iWe,iAddr,iWdata,oRdata);

input iClk; 		// clock
input iWe;		// write enable
input [7:2] iAddr;	// adrress
input [31:0] iWdata;	// write data
output [31:0] oRdata;	// read data

reg [31:0] RAM[63:0];

initial
begin
	RAM[0] = 32'b00000000000000000001000000100000;	// add $t1, $zero, $zero
	RAM[1] = 32'b00111000000000010000000000000001;	// ori $t0, $zero, 1
	RAM[2] = 32'b00111000000001110000000000010000;	// ori $t6, $zero, 16

	RAM[3] = 32'b00000000010000010001000000100000;	// for : add $t1, $t1, $t0
	RAM[4] = 32'b10101100010000100000000000000000;	// sw $t1, 0($t1)
	RAM[5] = 32'b00000000010001110010000000101010;	// slt $t3, $t1, $t6
	RAM[6] = 32'b000100_00001_00100_1111111111111100;	// beq $t3, $t0, for (move -4)

	RAM[7] = 32'b00000000000000000001000000100000;	// add $t1, $zero, $zero
	RAM[8] = 32'b00111000000001010000000000000000;	// ori $t4, $zero, 0

	RAM[9] = 32'b00000000010000010001000000100000;	// loop : add $t1, $t1, $t0
	RAM[10] = 32'b00000000101000100010100000100000;	// add $t4, $t4, $t1
	RAM[11] = 32'b00000000010001110010000000101010;	// slt $t3, $t1, $t6
	RAM[12] = 32'b000100_00001_00100_1111111111111100;	// beq $t3, $t0, loop (move -4)

	RAM[13] = 32'b10101100000001010000000000010001;	// sw $t4, 17($zero)
end

assign oRdata = RAM[iAddr[7:2]];

always @ (posedge iClk)
begin
	if (iWe)
		RAM[iAddr[7:2]] <= iWdata;
end

endmodule